1. Field of the Invention
The invention relates generally to the planarization of integrated circuit surfaces. More particularly, it relates to a chemical mechanical polishing process to prevent electrical shorts between tungsten interconnects.
2. Description of the Related Art
Semiconductor fabrication generally comprises providing tungsten or copper wiring or metallization in discrete layers of dielectric oxide film. Oxides typically used to form these film layers include phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) or silicon dioxide. The oxide layer is then planarized using conventional planarization techniques. Thereafter, the oxide layer is etched or otherwise processed to pattern a series of trenches and holes therein. A thin liner film, generally not more than approximately 1,000 Angstroms thick is then deposited over the oxide layer. The liner generally comprises thin films of titanium (Ti) and titanium nitride (TiN) disposed over one another to form a Ti/TiN stack, or tantalum (Ta) and tantalum nitride (TaN) to form a Ta/TaN stack. Such a liner is commonly deposited by physical vapor deposition (PVD), otherwise known as sputter deposition, or it may be deposited by a chemical vapor deposition (CVD) to form a more conformed coating. Accordingly, the liner serves to coat the surfaces of the trenches and holes as well as the upper surface of the oxide layer and is used to provide good adhesion between the metallization layer and the oxide layer. The metallization is then provided by depositing a layer of tungsten (W) or copper (Cu), in the range of approximately 3,000-11,000 Angstroms thick, over the liner layer, wherein the W or Cu will completely fill the trenches and holes. Fabrication of the wiring layer is then completed by removing the liner film and the tungsten or copper layer from the surface of the oxide film. This is typically accomplished by the use of Chemical Mechanical Polishing (CMP). The CMP process involves holding the semiconductor material against a rotating polishing pad surface under controlled downward pressure. A polishing slurry such as a mixture of either a basic or acidic solution used as a chemical etch component in combination with alumina particles used as an abrasive etch component may be used. A rotating polishing head or wafer carrier is typically used to hold the semiconductor wafer under controlled pressure against a rotating polishing platen. The CMP process effectively removes the tungsten layer, however removal of the liner film has proven to be problematic. The liner is difficult to remove, tending to remain behind in localized topography caused by prior level damascene dishing/erosion, and in unplanarized features or defects such as scratches. In addition, while attempting to remove the remnants of this liner film, the relatively abrasive alumina based slurry used in the CMP process tends to damage the oxide layer by scratching and pitting the surface thereof. It is thus common practice to continue the CMP process until substantially all of the liner has been removed from the surface of the oxide, and then employ a second step commonly known as an “oxide touch up.” This second step attempts to remove any residual liner material which may result in undesirable electrical shorts between tungsten interconnects, and replanarize the surface of the oxide to remove the scratches and other defects therein created by the CMP process. This oxide touch up step typically removes between 10 and 100 nanometers (nm), or between 100 and 1000 Angstroms of oxide.
This two-step approach, however, is not without significant drawbacks. In particular, the oxide touch up step is not always effective in removing the residual titanium and thus can cause additional erosion of the oxide layer, particularly in high pattern factor areas, or areas having a high density of metallization. In addition, the alumina-based slurry typically used in the CMP process is acidic whereas the oxide touch up chemical system is generally basic, wherein interaction between the two chemical systems can generate precipitates which complicate cleaning the slurry from the wafers. Moreover, the redundancy of planarizing the oxide surface a second time adds expense to the fabrication process while providing an opportunity for the introduction of further defects to the oxide surface. Thus, a need remains for an improved method of removing the tungsten or copper layer and a Ti/TiN or Ta/TaN liner film from the surface of an oxide layer which does not require an oxide touch-up step to essentially replanarize the surface of the oxide.